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Core are trademarks of Altera Corporation 9 n n Cascade modes - Input cascade - Output cascade Rounding - Unbiased and biased Saturation - Asymmetrical and symmetrical Barrel shifter - Arithmetic, logical, and rotation The Stratix DSP Block Evolution n n n © 2008 Altera Corporation-Public Output register unit Optional RND and SAT unit R Output multiplexer +-S + Output multiplexer R 72 ++ - Confidential +- + 72 R n Basic Multiplier Modes - 8 x (9 x 9) - 4 x (18 x 18) - 1 x (36 x 36) - 1 x complex (18 x 18) Accumulation - 2 x Acc Rounding - 16 -/32 -bit biased Saturation - 32 -bit asymmetrical Barrel shifter - Partial support Optional pipelining n +- +-S Optional pipelining 144 Input register unit Output register unit +-S Output multiplexer Optional pipelining + 144 ++ - R Input register unit 144 +-S Input register unit Stratix II FPGA Output register unit Stratix IV and Stratix III FPGAs Basic multiplier modes - 8 x (9 x 9) - 6 x (12 x 12) - 4 x (18 x 18) - 4 x (18 x 36) - 2 x (36 x 36) - 2 x complex (18 x 18) Multiply and sum modes - 4 x sum of two (18 x 18) - 2 x sum of four (18 x 18) Accumulation - 2 x Acc Altera, Stratix, Arria, Cyclone, MAX, Hard.